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Clocking
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
23.7
Suggested PLL configurations
To simplify the PLL configurations, the MPC8309 might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs is configured separately.
The following table shows suggested PLL configurations for 33 and 66 MHz input clocks.
Table 63. Suggested PLL configurations
Conf No.
1
2
3
4
5
6
7
8
9
SPMF
0100
0010
0100
0101
0010
0100
0101
0010
0101
Core
PLL
0000100
0000100
0000101
0000101
0000101
0000110
0000110
0000110
0000101
CEPMF
0111
0111
0111
1001
0111
0111
1000
0011
0111
CEDF
0
1
0
0
1
0
0
0
0
Input Clock
Frequency
(MHz)
33.33
66.67
33.33
25
66.67
33.33
25
66.67
33.33
CSB
Frequency
(MHz)
133.33
133.33
133.33
125
133.33
133.33
125
133.33
166.67
Core
Frequency
(MHz)
266.66
266.66
333.33
312.5
333.33
399.96
375
399.96
416.67
QUICC
Engine
Frequency
(MHz)
233
233
233
225
233
233
225
233
233
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
71
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